I recently saw a post on Hackaday about a course in MIT where the students get to build an FMCW radar from mainly off-the-shelf components. I got pretty excited about it and immediately thought that I wanted to build a better one from scratch.
The design presented in this post is just the preliminary design, a lot of things might change as I go along.
I won’t go to too much detail in this chapter because you can find a lot of better references on FMCW theory from elsewhere. Basically an FMCW radar is a continuous wave radar that transmits frequency sweeps called “chirps“. The chirp then travels down to the target and gets reflected back. The received signal is then mixed with the transmitted signal and amplified. From the resulting signal you can deduce distance to the target and how fast it is moving in relation to the radar (due to doppler shift). You can track multiple targets with just a single radar.
You can also use an FMCW radar to capture so called SAR (Synthetic Aperture Radar) images where either the radar moves in relation to the target or the target moves in relation to the radar (inverse SAR) which enables the radar to form a 3D-image of the target.
Applications of FMCW radars vary widely from military applications (target acquisition radars etc.), automotive radars, traffic counters and door openers to satellites. FMCW radars in satellites are used to measure ocean salinity, wind speed and wave height over water, soil moisture, geography etc.
I started off by making a block diagram of my design. I decided to make the radar for the 4.2-4.4GHz band because it has less interference than the 2.4GHz ISM band and the antennas will be smaller. In a nutshell there is a board with a PLL and a 2GHz VCO that gets doubled to 4GHz and amplified and transmitted with a 13dBi horn antenna. The return signal is received with the same kind of antenna. The received signal is then mixed with the transmitted signal, amplified with a transistor cascode amplifier and then amplified even more with two separate op-amp stages.
The idea was to make it modular, cheap and simple but most importantly well designed. I also tried to avoid using parts that are hard to find and/or expensive. One of the key design parameters in an FMCW radar is the phase noise performance. The lower the phase noise, the better. I have tried to make the phase noise as low as possible with several design choices.
The antennas are 13dBi horn antennas. I calculated the dimensions and then made a model of the antennas on SolidWorks. I’m looking in to getting the pieces lasercut from 0.5mm brass and soldering them together. The antennas have an adjustable end plate I can use to tune the antennas.
The signal source is based on a 2GHz VCO because they are readily available and cheap because they are widely used in cellular applications. The VCO is phase-locked with an ADF4158 PLL chip which is digitally controlled via a 3-wire interface.
This particular PLL chip is very handy because it has an integrated ramp generator needed to generate the chirps. The board has separate extremely low noise voltage regulators (ADP150) for all the different sections to try to reduce the noise. The traces going from the PLL to the VCO loop filter are shielded with ground fills and a LOT of vias to stop induced noise in the traces. Even very small amounts of noise on the traces can generate a lot of phase noise which is detrimental to the performance.
One of the hardest parts of this project is to get the PLL loop filter values correct to get a good linear sweep response.
The band-pass filter is situated after the multiplier. It is used to “select” the second harmonic from the amplifier output and attenuate the 1st and 3rd harmonics. It will most likely be implemented as a fifth order hairpin filter on Taconic TLC-30 PTFE laminate (which I have quite a lot). I have done hours and hours of simulations with Agilent ADS and I have a couple of different designs I am going to try. I’m guessing getting it to work correctly might be more difficult than I have anticipated! Getting the filter to work right will most likely require a few tries and a lot of measurements with a network analyzer.
Power splitter is just a regular resistive power splitter with ERA-5 MMIC amplifier stages on both outputs. Each amplifier has its own regulator.
The receiver has a HMC219MS8 GaAs passive double-balanced mixer. The IF signal from the mixer is amplified with a transistor cascode amplifier. The IF signal path is shielded with vias from induced noise. After the cascode the signal is amplified with two separate op-amp stages. The first stage acts as a range emphasis amplifier in which the the gain varies as a function of the frequency so that higher frequency signals (=target is far) are amplified more than low-frequency signals. The second op-amp amplifier acts as a low-pass filter with gain.
The signal from the receiver will be sampled in some way and processed on a computer. I will most likely use a sound card as the ADC at first but switch to a dedicated ADC board after I get my software working. The ADC will be housed with the microcontroller that will be controlling the PLL.
I started programming my own software for controlling the radar and displaying the video signal and FFT of the video signal. It uses Python, PyQt, guiqwt and SciPy/Numpy. It’s not too useful yet so it will need some work.