HardHeat Lock-On
HardHeat · FPGA induction heater controller · closed-loop simulation

Locking onto a 95 kHz tank in half a millisecond

The all-digital PLL starts at the top of its tuning range, sweeps down towards resonance and holds the drive just above it, with the tank current lagging the bridge voltage slightly so the bridge switches softly. Every number and curve on this page comes from the RTL running in the NVC simulator, closed around a series resonant tank model.

System architecture

One clock domain, one loop through the tank

The Cyclone V runs everything at 100 MHz from a PLL. The power path is pure logic so it reacts within clock cycles; the NIOS II processor only configures it through a register interface and supervises it. The phase-locked loop is closed outside the chip: the bridge drives the tank, a comparator turns the tank current back into a logic signal.

Block names are the VHDL entities in src/. The bold path is the PLL loop; the protection interlock and the register interface sit beside it.
Acquisition

From 125 kHz down onto resonance

Starting above resonance keeps the tank inductive, so the current is small at first and grows as the drive approaches the resonant frequency. The loop filter output and the phase error measured by the time-to-digital converter show the PLL doing the work.

DCO frequency (from the tuning word) tank resonance tank current amplitude
Move over the chart to read values.
The first 1.6 ms after reset. The phase error is one TDC reading per half-cycle; it settles at the phase setpoint of −350 ns, the current lagging the DCO edge. Markers A to C are the snapshots below; D is taken after lock_out rises.
Power control

Enhanced pulse density modulation

The bridge always switches at the resonant frequency the PLL found. Power is set by how many half-cycles of a 12 half-cycle frame it actually drives. The others are zero-voltage half-cycles: both low-side switches stay on, the tank current keeps ringing through them and no energy flows in. The H-bridge has three states for this:

LH LL RH RL bridge output voltage zero-voltage half-cycle
Gate signals from the FPGA pins and the resulting bridge voltage over one 12 half-cycle frame for each level, recorded in the closed-loop simulation. Levels follow V. Esteve et al., IEEE Trans. Industrial Electronics 62(11), 2015. The current is the mean peak over the frame.
What the simulation found

Found in simulation, and what is still open